We address the fundamental scaling issues of current AI hardware by shifting the paradigm from "synapse-heavy" architectures to physics-based dimension reduction. Our research focuses on Dendrocentric Computing, utilizing multi-gate devices (e.g., FeFET, Flash) to create ultra-compact decision-making nodes. 

In addition, by utilizing the intrinsic physical properties of semiconductor devices, we develop high-efficiency hardware for:

• Temporal Kernel & Reservoir Computing

• In-sensor Computing for real-time edge intelligence  

As modern data becomes increasingly interconnected, traditional hardware architectures struggle with graph-based workloads. We develop next-generation devices and architectures that physically represent graph structures. By utilizing the "least-resistance path" of current flow, our hardware can autonomously analyze complex network connectivity. This approach aims to solve large-scale graph problems and combinatorial optimization challenges for various real-world applications.

We explore the convergence of biological interfaces and advanced semiconductor devices. Our work involves mapping spatiotemporal data from bio-interfaces onto hardware to represent and analyze network structures in real-time. Furthermore, we develop Room-Temperature Quantum-inspired Computing systems. By exploiting the physical characteristics of emerging memory devices, we implement scalable, high-performance computing that achieves quantum-like functionality without the need for cryogenic environments.